Rice University logo
 
Top blue bar image Educational Technologies
 

Webcast Event Details

CMOS Process Variations: A "Critical Operation Point" hypothesis
Professor Janak H. Patel, Electrical and Computer Engineering, University of Illinois at Urbana-Champaign
 
date:4:00PM   US Central (GMT −0500)
Thursday, November 17, 2011
 
location:Duncan Hall Rice University
 
sponsor:ECE Distinguished Lecture Series
 
summary:

A brief overview of present and future CMOS process variations will be presented. Prevailing understanding of a chip’s behavior under large process variations with statistical delay assumptions leads one to conclude that a small number of errors are likely as we progress further down on Moore’s Law. This understanding is challenged by a new hypothesis on the behavior of very large CMOS chips in the presence of process variations. A Thought Experiment is presented which leads to the new hypothesis. The new hypothesis states that in every large CMOS chip, there exist critical operations points (frequency, voltage, temperature) such that it divides the 3-D space (F, V, T) in to two distinct spaces: 1. Error-free operation and 2. Massive errors (i.e. completely inoperable). Two attempts at disproving this hypothesis with real physical experiments will be described. Some consequences of the hypothesis on power savings in large data centers are also suggested.

 
more info:Lecture Webpage
 
watch:Click an available format icon to retrieve the archived webcast:
win logo     real logo         mp3 logo     mp4 logo